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Princeton Technology Corp.
MP3 Audio Decoder Description
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PT8401
The PT8401 is a single chip MPEG audio decoder capable of decoding all layers compressed elementary streams, as specified in MPEG 1 and MPEG 2 ISO standards. With external A/D converter, it can also compress incoming signal by using ADPCM algorithm, therefore it can also playback ADPCM bitstream.
Features
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?? ?? ?? ?? ?? ?? ?? ?? ?? ??
Supports all the sampling frequency of MPEG1 (32/44.1/48KHz), MPEG2(16/22.05/24KHz) and MPEG2.5 Serial Bit Stream Input Interface I2S/Normal Audio Data Output Format delivered via an Serial Bus Power Saving Mode Support Supports DAC Master Clock (256*fs / 384*fs for 16 / 24 bit DAC) Built-in Tone and Digital Equalizer Control Bass Booster Function 3D Sound Effect Function Pause Function Fast Forward Function Available in 44-pin Plastic LQFP Package
Applications
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Portable MP3 Player (Flash Memory Type) PDA with MP3 Player Cellular Phone with MP3 Player Hard Disk MP3 Player (IDE Interface) CD MP3 Player Digital Voice Recorder
PT8401 v 1.3
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Updated March 2002
Princeton Technology Corp.
MP3 Audio Decoder Block Diagram
?P
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PT8401
Host Interface ROM PLL RAM DSP Core Frame Buffer
Bitstream Input
Output Buffer Serial Interface
Audio Data
Figure 1: PT8401 Block Diagram
Typical Application Diagram
Flash Memory
Host ? P MP3 Decoder LCD Panel Key Pads Audio DAC
Figure 2: Typical Application Diagram
PT8401 v 1.3
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MP3 Audio Decoder Pin Configuration
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PT8401
DSPRDY
PWRDWN V SS
MCLKO
GPIO0
GPIO1
GPIO2
FILT PV SS
44 43 42 41 40 39 38 37 36 35 34 PA V D D 1 PA V SS 2 IIC C 3 IIC D 4 V DD 5 CLKI 6 V SS 7 TE 8 / RST 9 PD _R E Q 10 N C 11 12 13 14 15 16 17 18 19 20 21 22 GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO6 PD_ACK PD_ENA TEST1 GPIO9 33 G PIO 4 32 B C K 1 31 B _E N A 1 30 B D 1 29 V SS
GPIO3 28 V D D 27 G PIO 5 26 A C K Q O 25 A L R Q O 24 A D Q O 23 G PIO 8
PV DD
M P3 D ecoder
Figure 3: PT8401 Pin Configuration
PT8401 v 1.3
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Princeton Technology Corp.
MP3 Audio Decoder Pin Description
Pin Name PAVDD PAVSS IICC IICD VDD CLKI VSS TE /RST PD_REQ NC GPIO6 PD_ACK PD_ENA TEST1 GPIO15/DATA_REQ GPIO14 GPIO13 GPIO12/ACKQI2 GPIO11/ALRQI2 GPIO10/ADQI2 GPIO9 GPIO8 ADQO ALRQO ACKQO GPIO5 VDD VSS BD1 B_ENA1
PT8401 v 1.3
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PT8401
I/O Power Power I/O I/O Power I Power I I O I/O O I I I/O I/O I/O I/O I/O I/O I/O I/O O O O I/O Power Power I I
Description Analog Supply Positive for PLL Analog Supply Ground for PLL I C Clock Line I C Data Line Digital Supply Positive Clock Input Digital Supply Ground Test Enable Reset Parallel Data Request No Connection General Purpose IO 6 Parallel Data Acknowledge Signal Parallel Data Enable Transmission Test Pin. It is advisable to connect to Digital Ground General Purpose IO15 or Data Request General Purpose IO14 General Purpose IO13 General Purpose IO12 or Second Serial Input Clock General Purpose IO11 or Second Serial Input Frame Identification General Purpose IO10 or Second Serial Input Data General Purpose IO9 General Purpose IO8 Serial Output Data Serial Output Frame Identification Serial Output Clock GPIO5 or Start-Up Configuration Digital Supply Positive Digital Supply Ground First Serial Input Data First Serial Input Frame Identification
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2 2
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Updated March 2002
Princeton Technology Corp.
MP3 Audio Decoder
Pin Name BCK1 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 MCLKO VSS PWRDWN_ DSPRDY PVDD PVSS FILT I/O I I/O I/O I/O I/O I/O O Power I O Power Power Passive
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PT8401
Description First Serial Input Clock General Purpose IO4 or Start-Up Configuration General Purpose IO3 or Start-Up Configuration General Purpose IO2 or Start-Up Configuration General Purpose IO1 or Start-Up Configuration General Purpose IO0 or Start-Up Configuration Master Oversampling Clock Output for DAC Digital Supply Ground Power Down Control Decoder Operation Ready Digital Supply Positive for PLL Digital Supply Ground for PLL Connect to Capacitor 820pF. Pin No. 32 33 34 35 36 37 38 39 40 41 42 43 44
Functional Description
System and Interface Description
PT8401 is capable of decoding MPEG audio bitstream through a serial data interface. With proper external A/D converter, it is capable of encoding audio signal by the ADPCM Method. The primary operating mode of PT8401 is divided into three sections: MP3 Decoder, ADPCM Encoder and ADPCM Decoder. MP3 Decoding Mode: The bitstream input may either be from the first serial bitstream interface or parallel bitstream interface depending on the SP_SEL command. After processing, the audio data is outputted through the serial output interface. The controller can get bitstream information through GPIO or I2C interface even while the process is still in operation. ADPCM Encoding Mode: By connecting additional A/D to the second serial data interface and by issuing several basic commands like SetMode and AdpcmMode via I2C or GPIO, PT8401 can start ADPCM encoding, bitstream output through GPIO. Please refer to the Start-up Configuration and GPIO Setting Section for detailed timing diagram.
PT8401 v 1.3
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MP3 Audio Decoder
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PT8401
ADPCM Decoding Mode : Same as MP3 Decoding Mode, except that the commands SetMode and AdpcmMode have to be set to ADPCM Decoding Mode. The basic operation modes of PT8401 are Stop and Play. After all the necessary commands are set properly (like SP_SEL , PLL setting etc.), PT8401 will enter decoding/encoding process by issuing a Play command at address 0x40 through I2C interface. Besides, the MP3 decoding, PT8401 offers two additional modes, namely: Pause and Fast Forward . The Pause Mode will stop MP3 decoding, wait for the PLAY command set to the other mode. If PLAY=0x01 is issued, PT8401 will resume playing from the broken point. The Fast Forward Mode is achieved with the help of command Fward_Num(number of frame to play) and Skip_Num(number of frame to skip.
Serial Audio Interface
SERIAL OUTPUT INTERFACE In the serial audio output interface, following signals are generated: MCLK : Master Clock, configured as 256fs or 384fs according to Mclk Sel command. ADQO: Serial Data Output ACKQO: Bit Clock Output, derived from MCLK ALRQO: Left/Right Channel Word Selection ACKQO ADQO ALRQO
15 14 13 12 11 43210 15 14 13 12 11 43210 15
Left Channel Right Channel
Figure 4: Serial Audio Output Timing
PT8401 v 1.3
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Updated March 2002
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MP3 Audio Decoder
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PT8401
The default output waveform is show in Figure 4. Each PCM sample consists of a 2's complement 16-bit MSB-first data and another 16 bits of blank data forming 32 bits data in each channel. ADQO is valid at the rising edge of ACKQO and the last bit of a sample is aligned with the edges of ALRQO. However, PT8401 offers 3-bit, eight combinations to fit different kinds of audio DACs via the start-up configuration or command registers. Bit 0 : 32/16 bits per sample selection. If 16-bit per sample is selected, each channel contains only 16-bit MSB first data.
0 1
Left Left
Right Right
Bit 1 : ALRQO Left Channel indicating Low/High selection. Bit 2 : Delay Selection. When this bit is set, the transition of ALRQO is one clock cycle earlier. This is called I2S format.
ALRQO 0 1
15 14 13 12 11
Left Channel Right Channel
43210 15 14 13 1211 43210
ADQO
15 14 13 12 543210 15 14 1312 543210
FIRST SERIAL BITSTREAM INPUT INTERFACE Serial Bitstream (regardless of whether it is an MPEG audio or ADPCM speech bitstream) comes from this port. The following three signals are needed to make a complete transfer. BD1: Serial Bitstream Data Input. BCK1: Bit Clock Input. B_ENA1: Serial Data Enable Signal, Active: Low DATA_REQ : Data Request Signal.
PT8401 v 1.3
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Updated March 2002
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MP3 Audio Decoder
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PT8401
Microcontroller can transmit bitstream via the following two types of connections. Please refer to the diagram below.
BCK1 BD1 B_ENA1
Data_valid Data_invalid Data_valid
OR
Data_valid Data_invalid
Figure 5: Timing of First Serial Bitstream Input Interface. The maximum bit rate of MPEG is 448kbps. Basically, the speed of input bitstream clock must be greater than 448KHz. An input bitstream clock of 1MHz is recommended. Since the microcontroller doesn' know when to start the bitstream transmission, the DATA_REQ signal is needed to act as the t bitstream transmission indicator. When DATA_REQ is "High", the microcontroller starts another new bitstream packet transmission. If the DATA_REQ is set to "Low" , bitstream transmission is terminated. Please refer to Figure 6.
DATA_REQ
Figure 6: Timing of DATA_REQ Signal SECOND SERIAL DATA INPUT INTERFACE This port is usually connected with the A/D Converter and is used for speech encoding. The timing of this port is the similar as that of the serial output interface, except that the signals of the Second Serial Data Input Interface are inputs. This port also can connect with various ADCs through the setting in the Start-up Configuration or command register SetSAI2. Two bits setting is described below : Bit 0 : ALRQI2 Left Channel indicating Low/High Selection. Bit 1 : Delay Selection. When this bit is set, the transition of ALRQI2 is one clock cycle earlier. This is called I2S format.
PT8401 v 1.3
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Princeton Technology Corp.
MP3 Audio Decoder
PARALLEL BITSTREAM INPUT INTERFACE
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PT8401
In addition to the serial interface, the microcontroller can also transmit bitstreams via parallel interface. Parallel Mode is set via the Start-up Configuration or command register SP_SEL. Parallel data transmission consists of the following signals: 1. PD_REQ : Parallel Data Request. A bundle of data may be requested and this is sent from PT8401. 2. PD_ENA : Parallel Data Enable. This means that the data in the data bus is valid. This is sent from microcontroller. 3. PD_ACK : Parallel Data Acknowledge. This means that the decoder has received one byte successfully. This is sent from PT8401. 4. P_DATA : Parallel Data Bus is GPIO[15:8]. The GPIO15 is MSB and GPIO8 is LSB. Due to some low speed transmission, the microcontroller may not be fast enough to know that PT8401 has closed communication. Please refer to the example described in Figure 6 wherein during the byte 7 transmission. In this example, PT8401 did not recognize an Acknowledge signal; thus, byte 7 was not transmitted correctly. In order to avoid instability, it is better not to set SP_SEL frequently.
PD_REQ PD_ENA PD_ACK P_DATA[7:0] B0 B1 B2 B6 B7 B8
Figure 7 : Parallel Data Transmission Timing
PT8401 v 1.3
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MP3 Audio Decoder
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PT8401
PLL
PLL circuit provides two internal clocks, one for DSP and the other for the audio interface. The DSP clock rate is twice that of the external clock while the audio interface clock rate is dependent on the external audio clock. In order to satisfy different frequency settings, the PLL clock is divided into two sets. PLLSet PLLfraction are used for all frequencies. The default PLL setting assumes that the input frequency is 16.9344MHz. However, other frequency is acceptable, too. Please refer tables below for more information. If frequency is not on the list, please contact to PTC. Table 1. Settings for input frequency 10 MHz. Register Name PLLSet PLLFraction Value 0x3c20 0x7f80
Table 2. Settings for input frequency 14.318MHz. Register Name PLLSet PLLFraction Value 0x3b30 0x7e88
Table 3. Settings for input frequency 14.725MHz. Register Name PLLSet PLLFraction Value 0x3930 0x7ed1
PT8401 v 1.3
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MP3 Audio Decoder
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PT8401
Table 4. Settings for input frequency 12.288MHz. Register Name PLLSet PLLFraction Value 0x3b28 0x7e5e
The sampling frequency of ADPCM encoding is controlled by Serial Input Port 2; however, the sampling frequency of ADPCM decoding is controlled via the setting of PLL. The microcontroller has to be set properly to get the right listening results. The default setting for ADPCM decoding assumes that sampling frequency is 8kHz; however, 11.025kHz and 12kHz are selectable, too.
Start-up Configuration and General Purpose IO
PT8401 offers another easy way to configure the basic start-up setting without using the external controller. It is called "Start-up" Configuration. GPIO pins are configured as input pins before RESET. After RESET, those values are latched to be the basic configuration of PT8401. After start-up, the GPIO pins are configured as output pins.
START-UP CONFIGURATION GPIO 0 1 2 3 4 5 6 7
PT8401 v 1.3
Name SetMode "0" : MPEG Mode "1" : ADPCM Mode
Description
AdpcmMode "0" : Bitstream Decoding "1" : Sample Encoding. SP_SEL Set_SAO[0] Set_SAO[1] Set_SAO[2] Set_SAI2[0] Set_SAI2[1]
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"0" : First Serial Port "1" : Parallel Input Port Selection (only in MPEG Decoding). Set Serial Output Port. Same as Main Function Selection.
Set Second Serial Input Port. Same as Main Function Selection.
Princeton Technology Corp.
MP3 Audio Decoder
GPIO PINS DURING MPEG DECODING GPIO Name 0 1 3,2 MPEG ID Layer Info Sampling Frequency Description "0" : MPEG2 "1" : MPEG1 "0" : Layer III. "1" : Layer I or Layer II. "00" : 44.1/22.05 kHz "01" : 48/24 kHz "10" : 32/16 kHz "11" : reserved.
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PT8401
4
FRAME SYNC_INFO
An indicator for frame sync information. The period between two sync info is less than 72 ms. The controller can treat this pin as a new frame is decoded or if decoder is dead. Or every time this pin go high, new ancillary is update and can be download via I2C interface. "0" : no error. "1" : CRC_error or bitstream error. Half second indicator. The period between two high signal is half second (No effect during parallel mode). "0": no request. "1": Ask for bitstream input.
5 6 15
CRC ERROR Half_second Demand Signal
GPIO PINS DURING ADPCM ENCODING GPIO 0 1 2 3 4 Name Enc_Dat[0] Enc_Dat[1] Enc_Dat[2] Enc_Dat[3] Enc_ENA MSB "0" : Disable Encoded Data Output "1" : Enable Encoded Data Output Description LSB, 4-bit data during ADPCM Encoding.
PT8401 v 1.3
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MP3 Audio Decoder
SPEECH ADPCM ENCODING TIMING
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PT8401
ALRQI2 Enc_ENA Enc_DAT[3:0] D1 D2 D3 DN D N +1 D N +2
Figure 8: Speech ADPCM Encoding Timing. In Figure 8, ALRQI2 assumes that the command register Set_SAI2 bit 0 is"0". If Bit 0 is set to "1", the signal ALRQI2 in Figure 8 should be inverted.
I2C Microprocessor Interface
PT8401 uses I2C interface for communication. I2C communicate with multi devices using only two lines; namely: IICD and IICC. The following control and status registers are accessible via I2C interface.
?? ??
S is a Start Bit (a start condition). Any transmission must start with it. Dev_addr is a 7-bit Device Address Identifier. Each device can only have one address. PT8401 is fixed at "0110100b".
?? ??
R/W issues a read or write operation A/A is an Acknowledge Bit. It is performed in the receiver and is used to inform the transmitter that the data is properly received or used to stop data transmission.
??
P is a Stop Bit. Any sequence must end with it.
The I2C write operation is a word (two-byte) writing mode, as described in Figure 8. Multi-byte write is
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MP3 Audio Decoder
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PT8401
allowable, but PT8401 only receives it and does nothing. PT8401 is capable of the following read operations: Word Read, Multi-byte Read and Repeat Address Read Modes. In the Repeat Address Read Mode, the last successful transmitted address is read again even if the decoder has not been informed of the address. This mode is usually used for the address 0x00, FrameCount, which maybe the most frequently requested address in all command registers. In PT8401, only the command AncillaryData is allowed to use the Multi-byte Read Mode. Since A, no acknowledge signal is controlled by the receiver (microcontroller) in the read mode, the microcontroller will receive repeated data after 3rd byte in other command registers in Multi-byte Read Mode.
Word Write
S
D ev_addr W
A
Sub_addr
A
hi gh_byt e
A
l _byte ow
AP
Word Read
S
D ev_addr W
A
Sub_addr
AS
D ev_addr R
A
hi gh_byte
A
l _byte ow
AP
Multi-byte Read
S
D ev_addr W
A
Sub_addr
AS
D ev_addr R
A
1st_byte
A
2nd_byt e
A
A
Last_byte
AP
Repeat Address Read
S
D ev_addr R
A
hi gh_byte
A
l _byt ow e
AP
Figure 9: Read and Write Sequence for I2C Protocol. POWER DOWN SETTING To enter the Power Down Mode, Pin 40 (PWRDWN_) must be set to "LOW' The DSPRDY pin . goes to low, this indicates that PT8401 is already been powered down. There are two types of Power Down Modes, namely: Sleep Mode and the Deep Sleep Mode. The Sleep Mode turns off the DSP clock and only preserves PLL clock. The Deep Sleep on the other hand turns off DSP and PLL clock. All the commands that have been previously set will preserved. PT8401' default is the sleep mode. s With the command Pwr_Dwn_Reg set to 0x04 before power down, deep sleep is achieved.
PT8401 v 1.3
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MP3 Audio Decoder
Command Registers
MAIN FUNCTION COMMAND
Address Register Name 0x40 Play Description
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PT8401
Default R/W 0x0 R/W
0/1: stop/run the current operation mode. After reset, the controller set necessary command, then set this bit to 1 to start decode. 2: Pause Mode. 3: Fast Forward Mode. 4: Second Fast Forward Mode Note:2,3,4 only work on MPEG Decoding Mode.
0x41
SetMode
0 : MPEG Decoding Mode. 1 : Start ADPCM Mode. 2 : PCM bypass from First Serial Port. 3 : PCM bypass from Second Serial Port.
0x0
R/W
0x42 0x43 0x44 0x45
ADPCMMode 0 : ADPCM Decoding Mode 1 : ADPCM Encoding Mode. Mute Volume SP_SEL 1 : Mute all output signals. Output Volume Control. The range is between 0 dB and -96dB(0x60). Serial/Parallel Input Selection. 0 : First Input Serial Port Input is selected. 1 : Input Parallel Port Input is selected. Note : After this bit is set, it is better to run Software Reset to prevent instability.
0x0 0x0 0x0 0x0
R/W R/W R/W R/W
0x46
Set_SAO
Serial Output Port Mode Setting. Bit 0 Bit 1 Bit 2 Bit 3 0 : 32 bits per sample mode. 1 : 16 bits per sample mode. 0 : ALRQ Signal. Left is "Low". 1 : ALRQ Signal. Left is "High". 0 : Relative Timing No Delay to ALRQ. 1 : Relative Timing One Delay to ALRQ. 0 : Data is Left Alignment. 1 : Data is Right Alignment
0x0
R/W
PT8401 v 1.3
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MP3 Audio Decoder
0x46 Set_SAO Bit 5:4
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PT8401
00 : ACQO is generated from the Internal Clock. 01 : ACQO is generated from the External Clock. 10 : MCLKO is generated from the External Clock. 0x0 R/W
0x47
Set_SAI2
Second Serial Input Port Mode Setting Bit 0 0 : ALRQ Signal. Left is "Low". 1 : ALRQ Signal. Left is "High". Bit 1 0 : Relative Timing No Delay to ALRQ. 1 : Relative Timing One Delay to ALRQ.
0x0
R/W
0x59
ADPCM_FS_SE ADPCM Decoding Mode Sampling Frequency Selection. L 0 : 11.025kHz. 1 : 12kHz. 2 : 8kHz
0x0
R/W
0x5a 0x5e 0x63 0x64
Soft_Reset Pwr_Dwn_Reg Fward_Num Skip_Num
Set to 1 to software reset, but all the command registers keep the setting values. Power Down Control Register. Fast Foward Mode, number of frame to be play Fast Foward Mode, number of frame to be skip
0x0 0x0 0x6 0x6
W W W W
PLL SETTING COMMAND
Address Register Name 0x48 MclkSel Description Master Oversampling Output Clock Selection. "0" : 256fs. "1" : 384fs. 0x4b 0x4c PllSet PllFraction PLL Control Parameter Setting. 15-bit PLL Fraction Parameter Setting. 0x3b28 0x7e5e R/W R/W Default 0x0 R/W R/W
PT8401 v 1.3
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MP3 Audio Decoder
TONE AND 3D CONTROL COMMANDS
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PT8401
Tone control is allowable. It ranges up to +-15 dB cut or enhancement for bass and treble filter with step size of 1.5 dB. Although overflow prevention is performed, under the Bass Enhancement Mode, the gain may be reduced so that overflow may be prevented in advance by issuing the prescale command. This would generate better listening results. The cut off frequency for bass filter is about 250Hz for MPEG1, 125Hz for MPEG2. The cut off frequency for treble filter is about 10kHz for MPEG1, 5kHz for MPEG2. The 3D Mode controls the 3D effect function. Please take note that if the 3D Mode is enabled, the tone and balance controls are disabled. Address 0x50 0x51 Register Name Tone3D Bass Description "0" : Enable Tone Control. "1" : Enable 3D Control. "0x1" to "0xa" with step size 1.5dB bass enhancement. Maximum up to 15 dB. "0xb" to "0x14" with step size 1.5dB bass attenuation.. Minimum down to -15 dB Default is" 0x0", no enhancement. "0x1" to "0xa" with step size 1.5dB treble enhancement. Maximum up to 15 dB. "0xb" to "0x14" with step size 1.5dB treble attenuation. Minimum down to -15 dB. Default is "0x0", no enhancement. Default 0x0 0x0 R/W R/W R/W
0x52
Treble
0x0
R/W
0x53 0x54
Prescale Prescale command to reduce overall gain. Range is between 0dB(0x0) and -96dB(0x60) s 3D_Effect Control the Depth of 3D' Effect. Range is between between 0dB(0x0) and -96dB(0x60)
0x0 0x3
R/W R/W
PT8401 v 1.3
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MP3 Audio Decoder
BALANCE CONTROL COMMAND
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PT8401
Balance control is implemented through 4 coefficients setting as shown in Figure 9.
Original L
Prescale Mix_LL Mix_LR
+
Volume
Final L
Mix_RL
Original R
Prescale
Mix_RR
+
Volume
Final R
Figure 10: Balance Control Relation.
Address Register Name 0x55 Mix_LL
Description Mix original left channel to output left channel with 0 dB to -96 dB(0x60). Default is 0x0. Mix original right channel to output left channel with 0 dB to -96 dB(0x60). Default is 0x60. Mix original left channel to output right channel with 0 dB to -96 dB(0x60). Default is 0x60 Mix original right channel to output right channel with 0 dB to -96 dB(0x60). Default is 0x0.
Default 0x0
R/W R/W
0x56
Mix_RL
0x60
R/W
0x57
Mix_LR
0x60
R/W
0x58
Mix_RR
0x0
R/W
PT8401 v 1.3
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MP3 Audio Decoder
STATUS REGISTER COMMANDS
Address Register Name Description
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PT8401
Default R/ W
0x00
Frame Count
Increase one every frame, but if the following condition happen, it clear to 0. 1.enter stop command , 2.crc check error. 3.bitstream error.
0x0
R
0x01
MPEG Header Info1
Bit 4..15 3 1:2
Item
Description Reserved
0x0
R
ID Layer
1:MPEG1 0:MPEG2 11 : Layer I 10 : Layer II 01 : Layer III 00 : reserved
0 0x02 MPEG Header Info2 Bit
Protection Item
0 : protected by CRC, 1 : don' t Description mpeg1 layer I mpeg1 Layer II mpeg1 layer III mpeg2 Layer I mpeg2 Layer II Layer III 0x0 R
12..15 Bit Rate Index(kbps)
PT8401 v 1.3
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MP3 Audio Decoder
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 10..11 Sampling frequency 00 01 10 11 9 8 Bit 6..7 Padding_bit Private bit Item mode 00 01 10 11 4..5 Mode_extension Stereo Joint_stereo Dual_channel Single_channel Layer I,II mode=joint_stereo Description 44.1kHz 48kHz 32kHz reserved Free 32 64 96 128 160 192 224 256 288 320 352 384 416 448 Free 32 48 56 64 80 96 112 128 160 192 224 256 320 384
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PT8401
Free 32 40 48 56 64 80 96 112 128 160 192 224 256 320 Free 32 48 56 64 80 96 112 128 144 160 176 192 224 256 Free 8 16 24 32 40 48 56 64 80 96 112 128 144 160
forbidden forbidden forbidden forbidden forbidden MPEG1 MPEG2
22.05kHz 24kHz 16kHz reserved
0xff
R
Layer III Intensity_ Ms_stereo Stereo
PT8401 v 1.3
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MP3 Audio Decoder
00 01 10 11 3 2 0..1 copyright original emphasis 00 01 10 11 0x03 Subband=4-31 Subband=8-31 Subband=12-31 Subband=16-31
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PT8401
Off On Off On Off Off On On
0:not protected, 1: protected 0:copy, 1:original Indicate which type of emphesis is used None 50/15 microseconds reserved CCITT J.17 R
NumAncillaryBits Current frame contain number of ancillary bits contain in current frame. Update in 0x0 every frame.
0x04. 0x05
AncillaryData Error Status
Current frame' ancillary data. Update in every frame. Maximum is 56 bytes. s Bit 0 : Set to 1 : indicates CRC check error. Bit 1 : Set to 1 means bitstream error. The following several condition may cause error : 1). Information in MPEG header point to "reserved" condition.(layer to "00", sampling frequency to "11"). 2). Bit rate index point to free and forbidden condition.
0x0 0x0
R R
Electrical Characteristics
Absolute Maximum Ratings Symbol VSUP TA Parameter Digital supply voltage Ambient Operating Temperature Pin Name VDD Min. 2.7 -10 Max. 4 85 Unit V ?C
Recommended Operating Conditions Symbol TA
PT8401 v 1.3
Parameter Ambient Operating
Pin Name
Min. Typ. Max. Unit 25 ?C
Updated March 2002
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MP3 Audio Decoder
temperature VSUP Digital supply voltage VDD 3.3
Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw
PT8401
V
INPUT LEVEL : Symbol VIH Parameter Pin Name Min. Typ. Max. Unit V VDD 2.7 3.3 4.0 0.6 0.8 1.0 2.7 3.3 4.0 Input high /RST,PD_ENA, 1.7 voltage @ VDD = PWR_DWN, IICC, 1.7 2.7V ~ 4V IICD, GPIO 1.9 Input low voltage @ VDD = 2.7V ~ 4V
VIL
OUTPUT LEVEL : Symbol VOH Parameter Output high voltage Output low voltage Pin Name ADQO,ALRQO, ACKQO,PD_REQ, PD_ACK,DSP_RDY ADQO,ALRQO, VSS+0.1 ACKQO,PD_REQ, VSS+0.1 PD_ACK,DSP_RDY VSS+0.1 Min. Typ. Max. VDD-0.1 VDD-0.1 VDD-0.1 Unit V VDD 2.7 3.3 4.0 2.7 3.3 4.0
VOL
Current consumption
At Ta = 0 to 70 , Symbol IDD IDD IDD Parameter Current consumption Pin Name All supply pins Min. Typ. 85 64 45 Max. Unit mA mA mA Test Conditions VDD = 4V VDD = 3.3V VDD = 2.7V
I2C Bus Characteristics Symbol
PT8401 v 1.3
Parameter
Pin
Min.
Typ.
Max.
Unit
Test Condition
Updated March 2002
Page 22
Princeton Technology Corp.
MP3 Audio Decoder
Name FI2C TI2C1 TI2C2 TI2C3 TI2C4 TI2C5 I C bus frequency I2C start condition setup time I2C stop condition setup time
2
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PT8401
IICC IICC, IICD IICC, IICD 250 250 600 600 80
400
Khz ns ns ns ns ns
@CLKI = 8Mhz @CLKI = 8Mhz @CLKI = 8Mhz @CLKI = 8Mhz @CLKI = 8Mhz @CLKI = 8Mhz @CLKI = 8Mhz @CLKI = 8Mhz, FI2C= 400Khz @CLKI = 8Mhz
I2C Clock low pulse IICC time I2C Clock high pulse time I2C data hold time before rising edge of clock I2C data hold time after falling edge of clock IICC IICC
TI2C6
IICC
80
ns
TI2COL1
I2C data output IICC, hold time after IICD falling edge of clock I2C data output setup time before rising edge of clock IICC, IICD
30
ns
TI2COL2
0
ns
PT8401 v 1.3
Page 23
Updated March 2002
Princeton Technology Corp.
MP3 Audio Decoder
t I2C4 t I2C3
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PT8401
H L
IICC
t I2C1 t I2C5 t I2C6 t I2C2
H L
IICD as input
t i2COL2
t I2COL1
H L
IICD as output
I2S Characteristics - Serial input
Symbol tBCK tBDSTP Parameter I S clock input clockperiod I2S data setup time before falling edge clock
2
Pin Name BCK1 BCK1, BD1
Min Typ.
Max. Unit ns
Test Conditions
10
3
ns
@ CLKI = 16.9344MHz, 44.1Khz/Stereo, 32 bits
tBDHD
I2S data hold BCK1, time after falling BD1 edge of clock
10
3
ns
PT8401 v 1.3
Page 24
Updated March 2002
Princeton Technology Corp.
MP3 Audio Decoder
Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw
PT8401
t CK B
BCK1
H L
H B_ENA1 L
BD1
H L t D STP B
t DHD B
I2S Characteristics - Serial output
Symbol tACK Parameter I S clock output frequency
2
Pin Name ACKQO
Min Typ. 354
Max. Unit ns
Test Conditions @ CLKI = 16.9344MHz, 44.1Khz/Stereo, 32 bits
tALR
I2S worst strobe hold time after falling edge of clock I2S data hold time after falling edge of clock
ACKQO, ALRQO
1
3
ns
tADQ
ACKQO, ADQO
1
3
ns
PT8401 v 1.3
Page 25
Updated March 2002
Princeton Technology Corp.
MP3 Audio Decoder
Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw
PT8401
t ACK
ACKQO
H L
ALRQO H L
t LR A
ADQO
H L
t DO A
Firmware Characteristics
Symbol Parameter Pin Min Name Typ. Max. Unit Test Conditions
Synchronization Times tmpgsync Synchronization on MPEG bitstreams 24 72 ms MPEG1 layer 3, 44.1Khz, 128Kbits/sec
Order Information
Valid Part Number PT8401 Package Type 44-pins, LQFP Package
PT8401 v 1.3
Page 26
Updated March 2002
Princeton Technology Corp.
MP3 Audio Decoder Application Circuit
Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw
PT8401
Crystal
/RST IICD IICC
MP3 Decoder
ACKQO ALRQO ADQO MCLKO
PT8401 v 1.3
Flash Memory
L
Host ? P
DAC
R
DATA_RQ BD1 B_ENA1 BCK1
MIC OP
ADQI2
ADC
ALRQI2 ACQI2
Page 27
Updated March 2002
Princeton Technology Corp.
MP3 Audio Decoder Package Information
Tel : 886-2-29162151 Fax: 886-2-29174598 URL: http://www.princeton.com.tw
PT8401
44 -Pin, LQFP Package (Body Size: 10x10 mm, Pitch: 0.80mm, THK Body: 1.40mm)
D D1 -DA A2 A1
E1
E
-A-
-B-
L1
e
1
b
c
-C2
SEATING PLANE
R1 R2 GAUGE PLANE
0.25mm
-H-
S
3
L
PT8401 v 1.3
Page 28
Updated March 2002

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